SRAM cells in general are random access memory cells that retain data bits in their memory as long as power is being supplied. SRAM is typically used in personal computers, workstations, routers, peripheral equipment and the like.
SRAM cells are composed of a pair of cross coupled inverters (a 1st IN and a 2nd IN) connected together to form dual (a first and a second) storage node outputs with opposing logic states. Therefore SRAM cells have two stable logic states. The first logic state includes a logic 1 and a logic 0 (1, 0) at the first and second storage node outputs respectively. The second state includes a logic 0 and a logic 1 (0, 1) at the same first and second storage node outputs respectively.
The storage nodes will be connected to a pair of pass gate transistors (a 1st PG and a 2nd PG), which are typically n-type transistors. Typically each inverter includes a p-type pull up transistor (PU) and an n-type pull down transistor (PD). One of the pass gate transistors is connected to a bit line (BL) and the other to a bit line bar (BLB) (herein collectively “the bit lines”). A word line (WL) enables the pass gate transistors to control data flow between the inverters and the bit lines during read and write operations.
Generally in a semiconductor SRAM cell, the four n-type transistors (i.e., the two PG and two PD) are Fin Field Effect Transistors (FinFETs) imbedded in n-type fins. Additionally, the two p-type transistors (the two PU) of the SRAM cell are FinFETs imbedded in p-type fins. Accordingly, these types of SRAM cells are often known as FinFET SRAM cells.
During a read operation, it is imperative that the data stored in the SRAM cells remain stable and should not be affected by the read operation itself. Additionally, during a write operation, the data stored in the SRAM cells must be accurately and stably overwritten by the data on the bit lines. Data errors due to instability during a read or write operation are known as soft errors.
Several parameters can affect SRAM stability. However, two of the most important parameters that affect SRAM stability are the well-known Beta and Gamma ratios. Basically, the two ratios can be expressed as:Beta ratio=(Ion_PD)/(Ion_PG); andGamma ratio=(Ion_PG)/(Ion_PU);wherein:                Ion_PD is the mean drive current flow through the pull-down transistor;        Ion_PG is the mean drive current flow through the pass gate transistor; and        Ion_PU is the mean drive current flow through the pull-up transistor.        
To achieve good stability during a read operation the pull-down transistor must have a larger mean drive current than the pass gate transistor. Therefore, the Beta ratio must be greater than 1, and should be substantially greater than 1 if possible. To achieve good stability during a write operation, the pass gate transistor must have a larger mean drive current than the pull-up transistor. Therefore, the Gamma ratio must also be greater than 1, and should be substantially greater than 1 if possible.
However, it is also a well-known that the pull-up transistor should have as large a mean drive current as possible in order to achieve good stability during read and write operations. Therefore, in conventional prior art SRAM cells, the mean drive currents of the pull-down, pass gate and pull-down transistors will not be far apart.
Problematically, to achieve good stability in conventional prior art SRAM cells, the requirements of a high Beta ratio, a high Gamma ratio and a large mean drive current pull-up transistor are closely related. As such, it is difficult to achieve all three without tradeoffs in performance.
Also problematically, unavoidable manufacturing variations (such as variations in critical dimensions of the fins, spacers, channel widths and more) will affect the Beta ratio, Gamma ratio and transistor drive currents of large batch produced SRAM cells. This can lead to an increased probability of soft errors due to these manufacturing variations.
Accordingly, there is a need for an SRAM cell structure, and method of making the same, that can achieve a high Beta ratio during a read operation and a high Gamma ratio during a write operation for increased stability during both operations. Also, there is a need for an SRAM cell structure, and method of making the same, that has a stability that is less susceptible to manufacturing tolerances and variations.